1. Technical Field
This disclosure relates to computer systems, and more particularly, to caches in a computer system that are shared by multiple processing agents.
2. Description of the Related Art
Modern computer systems and processors therein typically include a number of different cache memories. A cache memory is a memory located in a memory hierarchy between registers (e.g., from where operands are fetched for the execution by execution units) and main memory (e.g., random access memory). Various levels of cache memory may be implemented, such as a level one (L1) cache, L2 cache, L3 cache, etc. The L1 cache may be the highest level cache, closest to the registers and execution units, with the L2 being at the next level down, and so on. A last level cache may be a cache that is closest to main memory within the memory hierarchy. When an execution unit needs data that is not already stored in a register, it may first query the L1 cache, then the L2 cache (if the data is not stored in the L1 cache) and so on. If the requested data is not stored in any cache, then the data may be accessed from memory, at a greater latency than with cache accesses.
Many modern processors and systems on a chip (SoCs) include multiple processor cores, i.e. multiple processors implemented on a common integrated circuit (IC) die. In such processors, multiple levels of cache memories may be implemented. Moreover, in some ICs having multiple processors implemented thereon, a last level cache (e.g., an L3 cache) may be shared by each of the processor cores.